System Structure & Program Execution

Reference: Ewha Womans University OS Lecture - Professor Ban Hyo-kyung

Computer System Structure

Mode bit

• What is Mode bit?

  • A protection mechanism to prevent a user program's incorrect execution from harming other programs and the operating system

• Why is Mode bit needed?

  • Because the operating system cannot control the CPU once it is handed over to a user program

  • An entity is needed to distinguish whether the operating system or a user program is executing machine instructions on the CPU

• Types of Mode bit

  Mode bit supports two modes of operation at the hardware level

  • 1 User mode

    • Executes user programs

    • Restricts the use of dangerous machine instructions (privileged instructions)

  • 0 Monitor mode (= Kernel mode, System mode)

    • Executes OS code

    • Important instructions (privileged instructions) that could compromise security can only be executed in monitor mode

• Mode bit transition method

  1. When an interrupt or exception occurs, the hardware sets the mode bit to 0

     • Interrupt refers to CPU Interrupt

       • from Disk controller, I/O controller, etc.

     • Exception refers to an exception that occurs when attempting to execute an unauthorized operation

  2. Before handing the CPU to a user program, the mode bit is set to 1

Registers

• What is a Register?

  • Attached to the CPU for the purpose of storing computation outputs

• Types of Registers

  • PC (Program Counter) Register

    • Holds the memory address of the next machine instruction to be executed

        == points to the address

    • The CPU executes the machine instruction at the memory address pointed to by the PC register

        → After execution, it executes the machine instruction at the next location

    • When a CPU Interrupt occurs, the memory that the PC Register points to becomes the OS

Timer

• What is a Timer?

  • The OS cannot take away CPU usage rights on its own

    → `Hardware` is needed to prevent CPU `monopolization`, and that is the Timer

• Role of the Timer

  • Generates an Interrupt to transfer control to the OS after a set amount of time has passed

    • Generates an Interrupt after a certain time to take away CPU usage rights

• How the Timer operates

  • The Timer decreases by 1 every clock tick

  • When the Timer value reaches 0, a Timer Interrupt occurs

  • Protects against a specific program monopolizing the CPU

Interrupt

• How Interrupts work

  • After saving the register and Program Counter at the point of the Interrupt, CPU control is handed over to the Interrupt handling routine

• Meaning of Interrupt

  • Interrupt (Hardware Interrupt)

    • An Interrupt generated by hardware

    • e.g.) An Interrupt raised by an I/O Controller

  • Trap (Software Interrupt)

    • Exception

      • When a program commits an error

      • Occurs when a program attempts to execute a privileged instruction

    • System Call

      • When a program calls a Kernel function

• Interrupt-related terminology

  • Interrupt Vector

    • Contains the address of the corresponding Interrupt handling routine

  • Interrupt handling routine

    (= Interrupt Service Routine, Interrupt Handler)

    • A Kernel function that handles the corresponding Interrupt

System Call

• What is a System Call?

  • A user program calling a Kernel function to receive OS services

  • The machine instruction for the CPU to request I/O is a privileged instruction

    • That is, a user program cannot execute it

        (Because privileged instructions cannot be executed when the mode bit is 1 in user mode)

    • So it must request the OS to do it

        → That is a System Call

  • A user program generating an Interrupt by itself is called a System Call

    • Since it cannot directly hand the Program Counter to the OS, it generates an Interrupt

Device Controller

• I/O Device Controller

  • A type of small CPU that manages the corresponding I/O device type

  • Has control register and status register for control information

    • control register

      • A register used to control and configure the operation of a processor or other hardware device

    • status register

      • A register that stores the current state and flag information of a processor

      • Primarily stores and controls information related to the processor's execution state, computation results, and Interrupt status

      • Flag types

        1. Zero Flag (ZF)

           1. Set when the computation result is 0

           2. Mainly used in relation to comparison operations

        2. Sign Flag (SF)

           1. Set when the computation result is negative

        3. Overflow Flag (OF)

           1. Set when an overflow occurs in the computation result

           2. Used in integer arithmetic

        4. Carry Flag (CF)

           1. Set when a carry occurs in the computation result

           2. Used in arithmetic operations

        5. Parity Flag (PF)

           1. Set when the number of 1s among the lower bits of the computation result is even

  • Has a local buffer (a type of data register)

• I/O occurs between the actual device and the local buffer

• The Device Controller notifies the CPU through an Interrupt when I/O is complete

• Terminology

  • Device Driver

    • Processing routines for each device in OS code → software

    • Machine instructions that the CPU uses to request the device controller

    • Code executed by the CPU inside the computer

  • Device Controller

    • A type of small CPU that controls each device → hardware

Cases When CPU is Handed Over to OS

CPU is handed over when an Interrupt occurs

1. When hardware devices generate an Interrupt

   → The true meaning of Interrupt

   • Timer

     • Hardware to prevent CPU monopolization

2. When a program directly sets the Interrupt line

   • System call

     • Exists because the machine instruction for the CPU to request I/O is a privileged instruction that user programs cannot execute

Sync I/O vs Async I/O

In both cases, I/O completion is notified through an Interrupt

• Synchronous I/O

  • After an I/O request, control is returned to the user program only after the I/O operation is completed

  • Implementation methods 1. Waste CPU until I/O finishes - Only one I/O can occur at any point in time 2. Take the CPU away from the program until I/O is complete, and put the program in the I/O waiting queue - Give the CPU to another program

• Asynchronous I/O

  • After I/O starts, control is immediately returned to the user program without waiting for the I/O operation to finish

DMA (Direct Memory Access)

• Used because fast I/O devices process at speeds close to memory

  → A device for directly accessing memory

• The device controller directly transfers the contents of the device's buffer storage to memory in block units without CPU mediation

• Generates interrupts in block units rather than byte units